The LPC4322 has a built-in USB PHY, so the schematic is simple: USB D+ and D- lines go directly to the MCU with 22-ohm series resistors and pull-up/pull-down configuration for device detection.
Ultimately, analyzing the J-Link V9 schematic reveals something slightly disappointing to hardware enthusiasts: The hardware is actually quite straightforward.
It is essentially a fast NXP MCU, a USB PHY, a decent oscillator, and a clean buffer stage. There is no "magic chip" that makes it fast. jlink v9 schematic
The magic is entirely in the firmware. Segger’s intellectual property lies in how they manage the JTAG state machine inside the LPC MCU, how they handle the USB packet overhead, and their proprietary RTT (Real-Time Transfer) technology. RTT uses a ring buffer in the target MCU's RAM that the J-Link reads via background memory access—this is a software innovation, not a hardware one.
There is a long-standing debate in the community: Does the J-Link V9 use an FPGA? The LPC4322 has a built-in USB PHY, so
Looking at the PCB layouts and "leaked" reference schematics:
If your goal is education, copying the J-Link V9 schematic is a fascinating exercise in PCB routing (USB highspeed and SWD signals require impedance control). However, if you need a functional debugger, consider legal open-source alternatives that have superb schematics available: These alternatives offer modern features (USB-C
These alternatives offer modern features (USB-C, high-speed SWD, multi-drop) without legal jeopardy.