set_output_delay -max 0.5 -clock core_clk [get_ports dout*] set_output_delay -min 0.1 -clock core_clk [get_ports dout*]
By: EDN Asia Technical Staff
Published: Q2 2021 synopsys design compiler tutorial 2021
In the high-stakes world of ASIC and FPGA design, the bridge between RTL (Register-Transfer Level) fantasy and gate-level reality is synthesis. For over three decades, Synopsys’ Design Compiler has been that bridge—the de facto standard for logic synthesis. The 2021 release (part of the 2021.03-SP3 family) didn’t reinvent the wheel; instead, it sharpened the axe. This feature explores the critical updates, workflow optimizations, and a hands-on tutorial to get you from Verilog to a timing-closed netlist faster than ever. set_output_delay -max 0
# Create a clock (Period 10ns = 100MHz)
create_clock -name clk -period 10.0 [get_ports clk]